1. Field of the Invention
The invention relates to a method for reading stored data from a resistive memory cell, in particular from a conductive bridging random access memory cell (or CBRAM memory cell). The invention further relates to a memory circuit comprising a resistive memory cell.
2. Description of the Related Art
In CBRAM memory circuits, information is stored in CBRAM memory cells each comprising at least one resistive memory element. The resistive memory element may acquire various resistance states wherein by setting the resistance state of the resistive memory element the information to be stored may be determined. In order to evaluate the content of the CBRAM memory cell, it is necessary to evaluate the resistive value of the resistive memory element of the respective memory cell. This may be carried out by applying a voltage and measuring the resulting current flowing through the CBRAM memory cell. So as not to change the resistance state of the resistive memory element while reading out the information, the voltages applied to the resistive memory element for this purpose must not be outside a certain voltage range, e.g., between 100 and 200 mV. Thereby, the resistance value of the resistance state of the resistive memory element is typically between 104 to 109Ω, resulting in currents flowing through the memory cells in the range between 100 ρA and 10 μA. In the circuitry typically used for CBRAM memory circuits, currents below 1 μA, however, cannot be resolved and are thus detected as 0 μA. In a single level design, i.e., in the case of a binary data storage within the CBRAM resistive memory cells, a potential sense amplifier would evaluate the current flowing through the memory cell by means of a reference current of 5 μA in order to differentiate between two logic states. In a multi-level design of the CBRAM memory circuit, the signalling current, which is already relatively low for CMOS circuitry, is further distributed to individual values. When storing 2 bits per memory cell, the cell currents amount to approximately 10 μA (state “11”), 6.66 μA (state “10”), 3.33 μA (state “01”) and 0 μA (state “00”), which requires a resolution of the signaling current of at least 1.66 μA, the realization of which is complex by means of conventional circuitry.
Thus, there is a need to provide a method for reading a memory datum from a CBRAM memory cell in which the above-mentioned disadvantages can be avoided and by means of which, particularly in a multi-level design, the detecting of the state of the resistive memory element of the CBRAM memory circuit can be carried out in a reliable manner. Furthermore, there is a need to provide a CBRAM memory circuit in which the information can be read from the CBRAM memory cells in an improved manner.